Low-Cost Allocator Implementations for Networks-on-Chip Routers

Cost-aware Topology Customization of Mesh-based Networks-on-Chip

Nowadays, the growing demand for supporting multiple applications causes to use multiple IPs onto the chip. In fact, finding truly scalable communication architecture will be a critical concern. To this end, the Networks-on-Chip (NoC) paradigm has emerged as a promising solution to on-chip communication challenges within the silicon-based electronics. Many of today’s NoC architectures are based...

A Review of Optical Routers in Photonic Networks-on-Chip: A Literature Survey

Due to the increasing growth of processing cores in complex computational systems, all the connection converted bottleneck for all systems. With the protection of progressing and constructing complex photonic connection on chip, optical data transmission is the best choice for replacing with electrical interconnection for the reason of gathering connection with a high bandwidth and insertion lo...

Processor allocator for chip multiprocessors

Low-cost hardware implementations for discrete-time spiking neural networks

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Spatial Parallelism in the Routers of Asynchronous On-chip Networks

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